1. Technical Field
The present invention relates to burn-in technology needed for reducing the early failure rate of semiconductor integrated circuit devices.
2. Description of the Related Art
In semiconductor integrated circuit devices (LSIs) such as memories and logics, as a technique for reducing the early failure rate (EFR), burn-in is performed for a sample that has been molded and sealed with a resin under a high temperature and a high voltage (for example, see JP-A-H11-83939).
However, in the burn-in process disclosed in page no. 6, FIG. 1 of JP-A-H11-83939, the burn-in stress applied to the sample cannot be acquired, and excessive burn-in stress may be applied. In addition, a dedicated part such as a burn-in board or a burn-in socket may be needed.